ATA8741-PXQW【PDF 108/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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108

9140CINDCO02/10

ATA8741

Figure 21-1. 16-bit Timer/Counter Block Diagram

21.2.1

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-

ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the

16-bit registers. These procedures are described in the section Accessing 16-bit Registers on

page 110. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all

visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the

Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk

The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun-

ter value at all time. The result of the compare can be used by the Waveform Generator to

generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See Out-

put Compare Units on page 116. The compare match event will also set the Compare Match

Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.

Clock Select

Timer/Counter

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA

TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

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